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rev. 0.7 1/14 copyright ? 2014 by silicon laboratories cp2130 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. cp2130 s ingle -c hip usb- to -spi b ridge single-chip usb-to-spi bridge ?? integrated clock; no external crystal required ?? integrated usb transceiver ; no external resistors required ?? integrated 348 byte one-time programmable rom for product customization ?? on-chip power-on reset circuit ?? on-chip voltage regulator: 3.45 v output ?? uses usb bulk mode transactions for high throughput - configurable priority for reads and writes usb peripheral function controller ?? usb specification 2.0 compliant; full-speed (12 mbps) ?? usb suspend states supported and indicated via suspend output pins usb interface ?? windows 8 ? , 7 ? , vista ? , and xp ? ?? open access to inte rface specification windows libraries ?? apis for quick application development ?? supports windows 8 ? , 7 ? , vista ? , and xp ? (sp2 & sp3) packages ?? rohs-compliant 24-qfn package (4x4 mm) spi controller ?? 3 or 4-wire master mode operation ?? configurable clock rate - 12 mhz, 6 mhz, 3 mhz, 1.5 mhz, 750 khz, 375 khz, 187.5 khz, 93.75 khz ?? clock phase and polarity control ?? chip select mode and toggle ?? programmable spi delay (post-assert, inter-byte, pre- deassert) 11 configurable gpio pins with alternate functions ?? usable as inputs, open-drain outputs, or push-pull outputs ?? up to 11 chip select outputs ?? ready-to-read pin allows for external signal to trigger spi read operations ?? ability to count edges or pulses using the event counter ?? up to 11 usb remote wakeup sources ?? spi activity indication (toggl es to indicate spi activity) ?? configurable clock output (93.75 khz to 24 mhz) supply voltage ?? self powered (regulator disabled): 3.0 to 3.6 v ?? self powered (regulator enabled): 3.0 to 5.25 v ?? usb bus powered: 4.0 to 5.25 v ?? i/o voltage: 1.8 v to v dd ordering part numbers ?? CP2130-F01-GM temperature range: ?40 to +85 c figure 1. example system diagram cp2130 48 mhz oscillator vbus d+ d- gnd usb connector logic level supply (1.8 v to vdd) multi-function signals usb interface peripheral function controller full-speed 12 mbps transceiver sck miso mosi vregin vdd gnd vio vbus d+ d- i/o power and logic levels gpio.6_cs6 gpio.5_cs5_clkout voltage regulator spi controller connect to vbus or external supply gpio vpp to spi slave devices multi- function signals to external circuitry gpio.0_cs0 gpio.1_cs1 gpio.2_cs2 gpio.3_cs3_rtr gpio.4_cs4_evtcntr 348 byte prom (product customization) gpio.7_cs7 gpio.8_cs8_spiact gpio.9_cs9_suspend gpio.10_cs10_suspend hardware reset spi chip select spi event counter clock output usb suspend spi activity spi readytoread remote wakeup reset
cp2130 2 rev. 0.7
cp2130 rev. 0.7 3 t able of c ontents section page 1. system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. usb function controller and transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1. signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2. data throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3. serial clock phase and polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. gpio pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1. gpio.3?ready-to-read (rtr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2. gpio.4?event counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3. gpio.5?clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4. gpio.8?spi activity indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.5. gpio.9-10?suspend and suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6. usb remote wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.7. gpio state during usb suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6. one-time programmable rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7. voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 8. cp2130 interface specificat ion and windows interface dl l . . . . . . . . . . . . . . . . . . . . .20 9. relevant application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 11. qfn-24 package specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 12. pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
cp2130 4 rev. 0.7 1. system overview the cp2130 is a highly-integrated usb-to -spi bridge controller providing a simp le solution for br idging a universal serial bus (usb) host to a serial peripheral interfac e (spi) bus using a minimum of components and pcb space. the cp2130 includes a usb 2. 0 full-speed controller, usb transceiver, oscillator, one-time programmable (otp) rom, and a spi controller in a compact 4 x 4 mm qfn24 package (sometimes called ?mlf? or ?mlp?). the on-chip, otp rom provides the option to custom ize the usb vendor id, product id, manufacturer string, product description string, power descriptor, device release number, device serial number, and gpio configuration as desired for oem applications. the cp2130 uses a silicon labs vendor-specific usb protocol using control and bulk tr ansfers which is supported by most operating systems through the use of generic usb drivers and interface libraries. a custom driver typically does not need to be developed for th is device. windows applications co mmunicate with the cp2130 through a windows dll which is provided by silicon labs that communicates with the microsoft winusb driver via a winusb dll. the interface specification for the cp2130 is also available to enable development of an api for any operating system that supports cont rol and bulk transfers over usb. the cp2130 spi implements the standard signals, including sck, miso, mosi, cs , as well as a ready-to-read (rtr) hardware handshaking input, so existing syst em firmware does not need to be modified. the spi capabilities of the cp2130 include fix ed spi clock rates ranging from 93.75 khz to 12 mh z, configurable clock phase, configurable clock polarity, adjustable spi dela ys, and up to 11 configur able chip select signals. any of the multi-purpose pins not used as chip select signals may instead be used as gpio signals that are user- defined. the gpio signals may also be configured to init iate a usb remote wakeup event on gpio state change, which allows the cp2130 to wake a usb host from sleep mode. eight of the gpio signals support alternate features including ready-to-read (rtr) handshaking, a co nfigurable event counter, a configurable clock output (93.75 khz to 24 mhz), spi activity led toggle, and usb suspend indicators. support for i/o interface voltages down to 1.8 v is provided via a v io pin. an evaluation kit for the cp2130 (part number: cp2130ek) is available. it includes a cp2130-based usb-to-spi evaluation board with spi sl ave devices such as an eeprom and adc as well as connections for an external cp2400 lcd controller evb and spi monitor. the kit also includes a windows dll a nd test application, usb cables, and full documentation. see www.silabs.com for the latest application notes and product support information for the cp2130. c ontact a silicon labs sales representatives or go to www.silabs.com to order the cp2130 evaluation kit.
cp2130 rev. 0.7 5 2. electrical characteristics table 1. global dc electrical characteristics v dd = 3.0 to 3.6 v, ?40 to +85 c unless otherwise specified. parameter symbol test condition min typ max unit digital supply voltage v dd 3.0 ? 3.6 v digital port i/o supply voltage v io 1.8 ? v dd v specified operating temperature range t a ?40 ? +85 c thermal resistance 1 ja ?28?c/w supply current usb suspended 2 i regin bus powered; regulator enabled ? 170 360 a self powered; regulator disabled; v dd =3.0v ? 170 290 a self powered; regulator disabled; v dd =3.3v ? 210 330 a usb normal; spi idle 2 bus powered; regulator enabled ? 14.4 18.8 ma self powered; regulator disabled; v dd = 3.0 v ? 13.8 18.1 ma self powered; regulator disabled; v dd = 3.3 v ? 14.1 18.4 ma usb normal; spi active 2 bus powered; regulator enabled ? 17.8 23.2 ma self powered; regulator disabled; v dd = 3.0 v ? 16.6 21.7 ma self powered; regulator disabled; v dd = 3.3 v ? 17.1 22.2 ma usb pull-up 3 i pu ?200230a notes: 1. thermal resistance assumes a multi-layer pcb with any exposed pad soldered to a pcb pad. 2. usb pull-up current should be added for total supply curre nt. usb normal and suspended supply current is current flowing into v regin . usb normal and suspended supply current is guaranteed by characterization. 3. the usb pull-up supply current values are calculated val ues based on usb specifications . usb pull-up supply current is current flowing from vdd to gnd through usb pull-down/pul l-up resistors on d+ and d-.
cp2130 6 rev. 0.7 table 2. spi, port i/o, and suspend i/o dc electrical characteristics v io = 1.8 to 3.6 v, ?40 to +85 c unless otherwise specified. parameters symbol test condition min typ max unit output high voltage v oh i oh = ?10 a, port i/o push-pull i oh = ?3 ma, port i/o push-pull i oh = ?10 ma, port i/o push-pull v io ?0.1 v io ?0.2 ? ? ? v io ?0.4 ? ? ? v output low voltage v ol i ol =10a i ol =8.5ma i ol =25ma ? ? ? ? ? 0.6 0.1 0.4 ? v input high voltage v ih 0.7 x v io ??v input low voltage v il ??0.6v input leakage current i l weak pull-up on, v in = 0 v ? 25 50 a maximum input voltage open drain, logic high (1) ? ? 5.8 v table 3. reset electrical characteristics ?40 to +85 c unless otherwise specified. parameter symbol test condition min typ max unit v dd ramp time t rmp time to v dd 2.7 v ? ? 1 ms rst input high voltage v ihreset 0.75 x v io ??v rst input low voltage v ilreset ??0.6v rst low time to generate a system reset t rstl 15 ? ? s table 4. voltage regulator electrical specifications ?40 to +85 c unless otherwise specified. parameter symbol test condition min typ max unit input voltage range 1 v regin regulator enabled v dd + v do ?5.25 v output voltage 2 v ddout output current = 1 to 100 ma 3.3 3.45 3.6 v vbus detection input threshold v busth 2.5 ? ? v dropout voltage v do 1ma i dd 100 ma ? 1 ? mv / ma bias current ? ? 120 a notes: 1. input range specified for regulation. when the internal regulator is not used, should be tied to v dd . 2. the maximum regulator supply current is 100 m a. this includes the supply current of the cp2130 .
cp2130 rev. 0.7 7 table 5. gpio output specifications ?40 to +85 c unless otherwise specified. parameter symbol test condition min typ max unit gpio.5 clock output * f clkout f clkout = configured frequency f clkout x 0.985 f clkout f clkout x 1.015 hz spi activity toggle rate f spiact ?10?hz *note: the clock output frequency is conf igurable from 93.75 khz to 24 mhz. table 6. usb transceiver electrical characteristics* v dd = 3.0 v to 3.6 v, ?40 to +85 c unless otherwise specified. parameter symbol test condition min typ max unit transmitter output high voltage v oh 2.8 ? ? v output low voltage v ol ?? 0.8 v output crossover point v crs 1.3 ? 2.0 v output impedance z drv driving high driving low ? ? 36 36 ? ? ? pull-up resistance r pu full speed (d+ pull-up) 1.425 1.5 1.575 k ? output rise time t r full speed 4 ? 20 ns output fall time t f full speed 4 ? 20 ns receiver differential input sensitivity v di | (d+) - (d-) | 0.2 ? ? v differential input common mode range v cm 0.8 ? 2.5 v input leakage current i l pullups disabled ? <1.0 ? a *note: refer to the usb specification for timing diagrams and symbol definitions. table 7. otp rom electrical characteristics ?40 to +85 c unless otherwise specified. parameter symbol test condition min typ max unit digital port i/o supply voltage during programming v io 3.3 ? v dd v voltage on v pp with respect to gnd during a programming operation v pp v io > 3.3 v 5.75 ? v io + 3.6 v capacitor on v pp for in-system programming ? 4.7 ? f
cp2130 8 rev. 0.7 table 8. thermal characteristics parameter symbol min typ max unit thermal resistance * ja ?28?c/w *note: thermal resistance assumes a multi-layer pcb with any exposed pad soldered to a pcb pad. table 9. absolute maximum ratings* parameter symbol test condition min typ max unit ambient temperature under bias t bias ?55 ? 125 c storage temperature t stg ?65 ? 150 c voltage on rst , gpio, or spi pins with respect to gnd v io > 2.2 v v io < 2.2 v ?0.3 ?0.3 ? ? 5.8 v io + 3.6 v voltage on vbus with respect to gnd v bus v dd > 3.0 v v dd not powered ?0.3 ?0.3 ? ? 5.8 v dd + 3.6 v voltage on v dd or v io with respect to gnd v dd ?0.3 ? 4.2 v maximum total current through v dd , v io , regin, and gnd ?? 500ma maximum output current sunk by rst or any i/o pin ?? 100ma *note: stresses above those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the devices at or exceeding the conditions in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
cp2130 rev. 0.7 9 3. usb function controller and transceiver the universal serial bus (usb) function controller in the cp2130 is a usb 2.0-compliant, full-speed device with integrated transceiver and on-chip matching and pullup re sistors. the usb function controller manages all data transfers between the usb and the spi bus as well as command requests generated by the usb host and commands for controlling the functi on of the spi and gpio pins. the usb suspend and resume modes are supported for power management of both the cp2130 device as well as external circuitry. the cp2130 enters suspend mo de when suspend signaling is detected on the bus. upon entering suspend mode, the suspend signals are asserted. the suspend signals are also asserted after a cp2130 reset until device configuration and u sb enumeration is comple te. suspend is logic high when the device is in the suspend state, and logic low when th e device is in normal mode. the suspend pin has the opposite logic value of the suspend pin. the cp2130 exits suspend mode when any of the following occur: resume signaling is detected or generated, a usb reset signal is detected, the configured gpio wakeup sources do not match the configured latch value, or a device reset occurs . suspend and suspend are weakly pulled to vio in a high impedance state during a cp2130 reset. if this behavior is undesirable, a strong pulldown (10 k ? ) can be used to ensure suspend remains low during reset. the cp2130 can be configured to use any of the gpio pi ns as a remote wakeup source. while suspended, if any of the pins configured as a wakeup source does not ma tch the configured wakeup match value, then the cp2130 will send remote wakeup signaling to the usb host. if the host has conf igured the cp2130 to enable remote wakeup, then the host will se nd resume signaling to th e cp2130 and the device will exit suspend mode. the logic level and output mode (push-pull or open-drain) of various pins during usb suspend is configurable in the otp rom. see section 6 for more information.
cp2130 10 rev. 0.7 4. serial peripheral interface (spi) the cp2130 serial peripheral interface (spi) provides ac cess to a flexible, full-duplex synchronous serial bus. the cp2130 can operate as a master device in both 3-wire or 4-wire modes, and supports multiple slaves. any of the 11 gpio pins may be configured as chip select ma ster outputs to select multiple spi slave devices. 4.1. signal descriptions the four signals used by spi (mosi, miso, sck, cs ) are described below. 4.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output from a master device and an input to slave devices. it is used to serially transfer data from the master to the slave. data is transferred most-significant bit first. 4.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output from a slave device and an input to the master device. it is used to serially transfer data from the slave to the master. data is transferred most-significant bit first. 4.1.3. serial clock (sck) the serial clock (sck) signal is an output from the ma ster device and an input to slave devices. it is used to synchronize the transfer of data between the master and slave on the mosi and miso lines. since the cp2130 always acts as a spi master, it always drives sck. 4.1.4. chip select (cs0 - cs10 ) the cp2130 may be used to control up to 11 different spi slave devices using gpio pins configured in chip select output mode. chip select signals are active low. see figure 2 and figure 3 for typical connection diagrams of the various operational modes. figure 2. 3-wire single master and 3-wire single slave mode connection diagram figure 3. 4-wire single master mode and 4-wire slave mode connection diagram master device miso mosi sck slave device miso mosi sck master device miso mosi sck slave device miso mosi sck slave device miso mosi sck cs cs cs1 cs0
cp2130 rev. 0.7 11 4.2. data throughput spi read and write data transfer throughput can be affected by many factors including usb host performance, host driver and pc application performance, spi clock rate, and data transfer size. also us b bulk transfers are limited by available bandwidth on the bus; increased traffic on the bus may decrease spi throughput. additionally, the cp2130 can be configured to operate in high-priority write or high-priority read mode. the priority mode is configured in the otp rom. the cp2130 has two independ ent usb endpoints used for bulk data transfers. the first endpoint is double buffered whereas the second endpoi nt is single buffered. each endpoint is used for only a single direction. a usb in transfer is data transferred from the device to the host. a usb out transfer is data transferred from the host to the device. more information about the usb interface can be found in application note, ?an792: cp2130 interface specification?. by default, the cp2130 is configured in high-priority wr ite mode, in which the double-buffered endpoint is used for out transfers and the single-buffered endpoint is used for in transfers. conversely, when the cp2130 is configured in high-priority read mode, the double-buffered endpoint is used for in transfers and the single-buffered endpoint is used for out transfers. table 10 below shows the cp2130 typical spi throughput in high-priority write and high-priority read modes using a 64-bit pc. 4.3. serial cloc k phase and polarity four combinations of serial clock phase and polarity can be selected using spi control commands over the usb interface. the clock phase (c pha) specifies which clock edg e is used to latch the data. the clock polarity (cpol) selects between an active-high or acti ve-low clock. both master and slave devices must be co nfigured to use the same clock phase and polarity. the clock and data line relationships are shown in figure 4. the spi clock field of the spi control command contro ls the master mode serial clock frequency. the clock frequency is restricted to discrete values between 93.8 khz and 12 mhz. figure 4. data/clock timing table 10. typical spi throughput device configuration conditions write throughput read throughput writeread throughput units high-priority write mode f sck =12mhz; block size = 64 kb 4.9 4.6 3.5 mbps high-priority read mode 4.2 6.6 2.9 mbps sck (cpha=leading ? edge, ? cpol=active ? high) sck (cpha=trailing ? edge, ? cpol=active ? high) sck (cpha=leading ? edge, ? cpol=active ? low) sck (cpha=trailing ? edge, ? cpol=active ? low) msb bit ? 6bit ? 5bit ? 4bit ? 3bit ? 2bit ? 1bit ? 0 miso/mosi
cp2130 12 rev. 0.7 figure 5. spi master timing (cpha=leading edge) figure 6. spi master timing (cpha=trailing edge) sck* mosi miso * ? sck ? is ? shown ? for ? cpol ? = ? active ? high. ?? sck ? is ? the ? opposite ? polarity ? for ? cpol ? = ? active ? low. t mih t mis sck ? shift ? edge 1 ? / ? f sck sck* miso mosi * ? sck ? is ? shown ? for ? cpol ? = ? active ? high. ?? sck ? is ? the ? opposite ? polarity ? for ? cpol ? = ? active ? low. t mis t mih sck ? shift ? edge
cp2130 rev. 0.7 13 figure 7. spi delays (cpha = leading edge) figure 8. spi delays (cpha = trailing edge) table 11. spi timing parameters 1 parameter symbol min typ max units sck frequency f sck 12 mhz 6mhz 3mhz 1.5 mhz 750 khz 375 khz 187.5 khz 93.75 khz miso valid to sck shift edge t mis 41.15 ? ? ns sck shift edge to miso change t mih 0??ns post-assert spi delay 2 t post-assert n x 10 s inter-byte spi delay 2 t inter-byte n x 10 s pre-deassert spi delay 2 t pre-deassert n x 10 s notes: 1. see figures 5?8. 2. n = user-specified delay values, where {0 n 65535}. sck* miso/mosi * ? sck ? is ? shown ? for ? cpol ? = ? active ? high. ?? sck ? is ? the ? opposite ? polarity ? for ? cpol ? = ? active ? low. cs t inter \ byte ? delay t post \ assert t pre \ deassert msb lsb msb lsb sck* miso/mosi * ? sck ? is ? shown ? for ? cpol ? = ? active ? high. ?? sck ? is ? the ? opposite ? polarity ? for ? cpol ? = ? active ? low. cs t inter \ byte ? delay t post \ assert t pre \ deassert msb lsb msb lsb
cp2130 14 rev. 0.7 5. gpio pins the cp2130 supports 11 user-configurable gpio pins. each of these gpio pins are usable as inputs, open-drain outputs, or push-pull outputs. each gpio pin may also be configured for use as spi chip select signals for up to 11 different spi slaves. six of these gp io pins also have alternate function s which are listed in table 12. more information regarding the configuration and usage of these pins is available in app lication note, ?an721: cp21xx customization guide? available on the silicon labs website. the default configuration for all of the gpio pins is provided in table 13. the configuration of the pins is one-time programmable for each device. see section 6 for more information about programming the gpio pin functionality. the difference between an open-drain output and a push-pul l output is evident when the gpio output is driven to logic high. a logic high, open-drain output pulls the pin to the v io rail through an internal, pull-up resistor. a logic high, push-pull output directly drives the pin to the v io voltage. open-drain outpu ts are typically used when interfacing to logic at a higher voltage than the v io pin. these pins can be safely pulled to the higher, external voltage through an external pull-up resistor. the maximum external pull-up voltage is 5 v. the speed of reading and writing the gpio pins is subjec t to the timing of the usb interface and host computer. gpio pins configured as inputs or outputs are not recommended for real-time signaling. the following paragraphs describe the alternate f unctions available on the corresponding gpio pin. table 12. gpio pin alternate functions gpio pin alternate function gpio.3 ready-to-read (rtr) gpio.4 event counter gpio.5 clock output gpio.8 spi activity gpio.9 suspend gpio.10 suspend table 13. gpio pin default configuration gpio pin default function gpio pin default function gpio.0 cs0 (push-pull output) gpio.6 gpio (input) gpio.1 cs1 (push-pull output) gpio.7 gpio (push-pull output) gpio.2 cs2 (push-pull output) gpio.8 spi activity (push-pull output) gpio.3 rtr active low (input) gp io.9 suspend (push-pull output) gpio.4 event counter rising edge (input) gpio.10 suspend (push-pull output) gpio.5 clock output (push-pull output)
cp2130 rev. 0.7 15 5.1. gpio.3?ready-to-read (rtr) rtr, or ready-to-read, is a configurable active-low or active-high input to the cp2130 and is used by the spi slave device to indicate to the cp2130 when to read. when performing a read with rtr command, the cp2130 will only read spi data when the rtr pin is asserted. by default, gpio.3 is configured to operate as the rtr in put pin. in addition to th e gpio otp rom configuration, the device must be configured to use rtr flow control to use this pin. figure 9. hardware flow control typical connection diagram 5.2. gpio.4?event counter gpio.4 is configurable as an event counter digital input pi n. the event counter can be configured to count edges or pulses. the four configurab le modes are: rising edge, falling edge, positive pulse, or negative pulse. once configured for event counter mode, the cp2130 maintains a 16-bit counter that increments by ?1? whenever the specified edge or pulse is detected. the user may query the cp2130 to get the current event count. the event counter can be used to detect slave interrupt events by connecting the slave interrupt output pin to the cp2130 event counter pin. 5.3. gpio.5?clock output gpio.5 is configurable to output a configurable cmos cl ock output. the clock output appears at the pin at the same time the device completes enumeration and exits u sb suspend mode. the clock output is removed from the pin when the device enters usb suspend mode. the output frequency is configurable through the use of a divider and the accuracy is specified in table 5. when the divider is set to 0, the output fre quency is 93.75 khz. for divider values between 1 and 255, the output fr equency is determined by the formula: equation 1. gpio.0 clock output frequency master device slave device rtr rtr sck sck mosi mosi miso miso gpio.5 clock frequency 24 mhz divider -------------------- - =
cp2130 16 rev. 0.7 5.4. gpio.8?spi activity indicator gpio.8 is configurable as a spi activity indicator pin. this pin is logic high when a de vice is not transferring data over the spi, and toggles at a fixed rate as specified in table 5 when a data transfer is in progress. typically, this pin is connected to an led to indicate data transfer. figure 10. spi activity toggle typical connection diagram 5.5. gpio.9-10?su spend and suspend gpio.9 and gpio.10 are conf igurable as active-high su spend and active-low suspend pins. the suspend pin is logic high when the device is in the suspended stat e and logic low when the device is in the active mode. the suspend pin has the opposite logic value of the suspend pin. 5.6. usb remote wakeup any of the gpio pins may be used to trigger a usb remote wakeup event. before the cp2130 enters the suspend state, the device may be configured to wakeup on a port mismatch event. when any of the pins specified in the wakeup mask do not match the pin logic value specified in the wakeup va lue, the cp2130 will wakeup and signal remote wakeup on the bus. the cp2130 will assert usb remote wakeup signa ling for 10 to 15 ms before the host may respond by resuming the cp2130. any gpio pin used for remote wakeup must be configur ed as an input during the sus pend state. gpio pins are selected as wakeup pins using the wakeup match mask. the wakeup match value specif ies the logic level of the wakeup pin. when the pin level does not match the valu e specified, the device will wakeup. the default wakeup match mask and wakeup match value are shown in table 15. 5.7. gpio state during usb suspend all gpio pins support programmable suspend state mo de and latch values. when the cp2130 enter usb suspend mode and the use suspend mo de and values option is set, the cp2130 will reconfigure the gpio pins just prior to entering usb suspend mode. when the cp2130 resumes from usb suspend mode, the gpio pins revert to the previous function configurations and modes. gpio.8 ? spi activity cp2130 v io
cp2130 rev. 0.7 17 6. one-time programmable rom the cp2130 includes an internal, otp rom that may be used to customize the usb vendor id (vid), product id (pid), manufacturer string, product description string, power descriptor, device re lease number, device serial number, gpio configuration, suspend pins and modes as desired for oem applications. if the otp rom has not been customized, the default configuration data shown in table 14 and table 15 is used. while customization of the usb confi guration data is optional, customizing the vid/pid combi nation is strongly recommended. a unique vid/pid will pr event the device from being reco gnized by any other manufacturer?s software application. a vendor id c an be obtained from www.usb.org or silicon labs can provide a free pid for the oem product that can be used with the silicon labs vid at www.silabs.com/requestpid . all cp2130 devices are pre-programmed with a unique serial number. it is importan t to have a unique serial string if it is possible for multiple cp2130 devices to be connected to the same pc. application note, ?an792: cp 2130 interface specification?, includes more information about the programmable values and their valid options. note that certain items in the otp rom are programmed as a group and programming one of the items in the group prevents furt her programming of any of the other items in the group. the configuration data otp rom is prog rammable by silicon labs prior to ship ment with the desi red configuration information. it can also be programmed in-system over the usb interface if a 4. 7 f capacitor is connected between the v pp pin and ground. no other circuitry should be connected to v pp during a programming operation, and v io must remain at 3.3 v or higher to succes sfully write to the configuration otp rom. table 14. default usb configuration data name value vendor id 0x10c4 product id 0x87a0 power descriptor (attributes) 0x80 (bus-powered) power descriptor (max. power) 0x32 (100 ma) release number 0x0100 (release version 01.00) transfer priority high priority write manufacturer string ?silic on laboratories? (62 ascii characters maximum) product description string ?cp2130 usb-to- spi bridge? (62 ascii characters maximum) serial string unique 8 character ascii string (30 ascii characters maximum) table 15. default gpio, uart, and suspend configuration data name value name value gpio.0 cs0 push-pull output use suspend mode and values false gpio.1 cs1 push-pull output suspend mode 0x0000 (open-drain) gpio.2 cs2 push-pull output suspend latch 0x0000 (logic low) gpio.3 rtr active low wakeup match mask 0x0000 (ignore all) gpio.4 event counter rising edge wakeup match value 0x0000 (match value logic low) gpio.5 clock output clock divider 0 (93.75 khz) gpio.6 gpio input gpio.7 gpio push-pull output gpio.8 spi activity push-pull output gpio.9 suspend push-pull output gpio.10 suspend push-pull output
cp2130 18 rev. 0.7 7. voltage regulator the cp2130 includes an on-chip 5 v to 3.45 v voltage regul ator. this allows the cp2130 to be configured as either a usb bus-powered device or a usb self-powered device . a typical connection diagram of the device in a bus- powered application using the regulator is shown in figure 11. when enabled, the voltage regulator output appears on the v dd pin and can be used to power external devices. see table 4 for the voltage regulator electrical characteristics. note: by default, the cp2130 is configured for bus-powered operat ion. the cp2130 otp configurat ion must be changed if the device will be operated in either of the self-powered modes. if the regulator is used to provide v dd in a self-powered application, use t he same connections from figure 11, but connect regin to an on-board 5 v supply, and disconnec t it from the vbus pin. in addition, if regin may be unpowered while vbus is 5 v, a resistor divider (or functiona lly equivalent circuit) show n in note 6 of figure 12 is required to meet the absolute maximum voltage on vbus specification in table 9. figure 11. typical bus-powered connection diagram note 4 suspend signals spi and gpio signals cp2130 mosi miso vpp suspend suspend vbus d+ d- rst vio 4.7 kohm note 5 notes: 1. vio can be connected directly to vdd or to a supply as low as 1.8 v to set the i/o interface voltage. 2. usb connector shield decoupling capacitors and re sistor are not required, but ca n be added for noise immunity. 3. avalanche transient vo ltage suppression diodes compatible with full-speed usb should be added at the connector for esd protection. use littelfuse p/n sp0503baht or equivalent. 4. an external pull-up is not required, but can be added for noise immunity. 5. if programming the configuration rom via usb, add a 4.7 ? f capacitor between vpp and ground. during a programming operation, do not connect the vpp pin to other circuitry, and ensure that vio is at least 3.3 v . 4.7 ? f note 1 regin vdd gnd vio 4.7 ? f0.1 ? f 3.45 v power 1 ? f0.1 ? f sck 0.1 ? f 0.1 ? f 1 mohm note 3 note 2 vbus d+ d- gnd usb connector shield gpio.0 / cs0 gpio.1 / cs1 gpio.2 / cs2 gpio.3 / cs3 / rtr gpio.4 / cs4 / evtcntr gpio.5 / cs5 / clkout gpio.6 / cs6 gpio.7 / cs7 gpio.8 / cs8 / spiact gpio.9 / cs9 / suspend gpio.10 / cs10 / suspend
cp2130 rev. 0.7 19 alternatively, if 3.0 to 3.6 v power is supplied to the v dd pin, the cp2130 can function as a usb self-powered device with the voltage regulator bypassed. for this configuration, tie the regin input to v dd to bypass the voltage regulator. a typical connection diagram showing the dev ice in a self-powered app lication with the regulator bypassed is shown in figure 12. the usb max power and power attributes descriptor must match the device power usage and configuration. see application note, ?an721: cp21xx customization guide?, fo r information on how to customize usb descriptors for the cp2130. figure 12. typical self-powered connection diagram (regulator bypass) note 4 suspend signals spi and gpio signals cp2130 gpio.0 / cs0 gpio.1 / cs1 gpio.2 / cs2 gpio.3 / cs3 / rtr mosi miso vpp suspend suspend gpio.4 / cs4 / evtcntr gpio.5 / cs5 / clkout gpio.8 / cs8 / spiact gpio.9 / cs9 / suspend gpio.6 / cs6 / mmack gpio.7 / cs7 / mmreq vbus d+ d- rst vio 4.7 kohm note 5 notes: 1. vio can be connected directly to vdd or to a supply as low as 1.8 v to set the i/o interface voltage. 2. usb connector shield decoupling capacitors and resistor are not required, but can be added for noise immunity. 3. avalanche transient voltage suppression diodes compatible wi th full-speed usb should be added at the connector for esd protection. use littelfuse p/n sp0503baht or equivalent. 4. an external pull-up is not required, but can be added for noise immunity. 5. if programming the configuration rom via usb, add a 4.7 ? f capacitor between vpp and ground. during a programming operation, do not connect t he vpp pin to other circuitry, and ensure that vio is at least 3.3 v . 6. for self-powered systems where vdd and vi o may be unpowered when vbus is connected to 5 v, a resistor divider (or functionally -equivalent circuit) on vbus is required to meet the abso lute maximum voltage on vbus specification in the electrical char acteristics section. 4.7 ? f gpio.10 / cs10 / suspend sck 0.1 ? f 0.1 ? f 1 mohm note 3 note 2 vbus d+ d- gnd usb connector shield note 1 regin vdd gnd vio 4.7 ? f0.1 ? f 1 ? f0.1 ? f 3.3 v power 47 k 24 k note 6 (optional)
cp2130 20 rev. 0.7 8. cp2130 interface specificati on and windows interface dll the cp2130 is a bulk mode usb device and requires a ge neric usb driver such as microsoft?s winusb driver or the open-source libusb driver. the cp2130 uses a vendor-spe cific interface protocol, and so the host application or library must comply with the cp2130 interface specif ication to communicate with t he device. the low-level usb specification for the cp2130 is prov ided in application note, ?an792: cp 2130 interface specification.? this document describes all of the basic functions for opening, reading from, writing to, and closing the device as well as the otp rom programming functions. silicon labs also provides an interf ace library that encapsulate s the cp2130 interface an d also adds higher level features such as read/write time-outs. this library is the recommended interface for the cp2130. the interface library is provided as a windows dll. documentation for the interface library api is included in the installation package. an792: cp2130 interface specification and the library are available in th e cp2130ek cd as well as online at: www.silabs.com. 9. relevant application notes the following application notes are applicable to the cp21 30. the latest versions of these application notes and their accompanying software are available at http://www.silabs.com/products/interface/p ages/interface-app lication-notes.aspx . ? an721: cp21xx device customization guide. this application note describes how to use the an721 software, cp21xx custom ization utility, to configure the u sb parameters on cp2130 devices. ? an792: cp2130 interface specification. this application note describes how to interface to the cp2130 using the low-level, usb bulk and control mode interface.
cp2130 rev. 0.7 21 10. pin descriptions figure 13. qfn-24 pinout diagram (top view) 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 18 17 16 15 14 13 gnd (optional) cp2130-gm top view gpio.3 / cs3 / rtr gpio.2 / cs2 gpio.1 / cs1 gpio.0 / cs0 mosi miso sck gnd d+ n/c gpio.10 / cs10 / suspend gpio.9 / cs9 / suspend gpio.4 / cs4 / evtcntr gpio.8 / cs8 / spiact gpio.7 / cs7 gpio.6 / cs6 vpp gpio.5 / cs5 / clkout vdd vio d- vbus regin rst
cp2130 22 rev. 0.7 table 16. cp2130 pin definitions pin # name type description 1 sck d out spi clock output 2 gnd ground. must be tied to ground. 3d+d i/ousb d+ 4d?d i/ousb d? 5v io power in i/o supply voltage input. 6v dd power in power out power supply voltage input. voltage regulator ou tput. see section 7. 7 regin power in 5 v regulator input. this pin is the input to the on-chip voltage regulator. 8 vbus d in vbus sense in put. this pin should be connected to the vbus signal of a usb network. 9rst d i/o device reset. open-drain output of internal power-on reset or v dd monitor. an external source can initiate a system rese t by driving this pin low for the time specified in table 3. 10* n/c no connect. this pin should be left unconnected or tied to v io . 11* gpio.10 cs10 suspend d i/o d out d out in gpio mode, this pin is a us er-configurable input or output. in chip select mode, this pin is a spi chip select output. in usb suspend mode, this pin is low when in usb suspend mode. 12* gpio.9 cs9 suspend d i/o d out d out in gpio mode, this pin is a us er-configurable input or output. in chip select mode, this pin is a spi chip select output. in usb suspend mode, this pin is high when in usb suspend mode. 13* gpio.8 cs8 spiact d i/o d out d out in gpio mode, this pin is a us er-configurable input or output. in chip select mode, this pin is a spi chip select output. in spi activity mode, this pin to ggles to indicate spi activity. 14* gpio.7 cs7 d i/o d out in gpio mode, this pin is a us er-configurable input or output. in chip select mode, this pin is a spi chip select output. 15* gpio.6 cs6 d i/o d out in gpio mode, this pin is a us er-configurable input or output. in chip select mode, this pin is a spi chip select output. 16* v pp special connect a 4.7 f capacitor between this pin and ground to support otp rom programming via the usb interface. *note: pin can be left unconnected when not in use.
cp2130 rev. 0.7 23 17* gpio.5 cs5 clkout d i/o d out d out in gpio mode, this pin is a us er-configurable input or output. in chip select mode, this pin is a spi chip select output. in clock output mode, this pin outputs a configurable frequency clock signal. 18* gpio.4 cs4 evtcntr d i/o d out d in in gpio mode, this pin is a us er-configurable input or output. in chip select mode, this pin is a spi chip select output. in event counter mode, this pi n is an event counter input. 19* gpio.3 cs3 rtr d i/o d out d in in gpio mode, this pin is a us er-configurable input or output. in chip select mode, this pin is a spi chip select output. in ready-to-read mode, this pin is a spi read flow control input. 20* gpio.2 cs2 d i/o d out in gpio mode, this pin is a us er-configurable input or output. in chip select mode, this pin is a spi chip select output. 21* gpio.1 cs1 d i/o d out in gpio mode, this pin is a us er-configurable input or output. in chip select mode, this pin is a spi chip select output. 22* gpio.0 cs0 d i/o d out in gpio mode, this pin is a us er-configurable input or output. in chip select mode, this pin is a spi chip select output. 23 mosi d out spi master output/slave input 24 miso d in spi master input/slave output table 16. cp2130 pin definitions (continued) pin # name type description *note: pin can be left unconnected when not in use.
cp2130 24 rev. 0.7 11. qfn-24 package specifications figure 14. qfn-24 package drawing table 17. qfn-24 package dimensions dimension min typ max dimension min typ max a 0.70 0.75 0.80 l 0.30 0.40 0.50 a1 0.00 0.02 0.05 l1 0.00 ? 0.15 b 0.18 0.25 0.30 aaa ? ? 0.15 d 4.00 bsc. bbb ? ? 0.10 d2 2.55 2.70 2.80 ddd ? ? 0.05 e 0.50 bsc. eee ? ? 0.08 e 4.00 bsc. z ? 0.24 ? e2 2.55 2.70 2.80 y ? 0.18 ? notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec solid state outline mo-220, variation wggd except for custom features d2, e2, z, y, and l wh ich are toleranced per supplier designation. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components.
cp2130 rev. 0.7 25 12. pcb land pattern figure 15. qfn-24 recommended pcb land pattern table 18. qfn-24 pcb land pattern dimensions dimension min max dimension min max c1 3.90 4.00 x2 2.70 2.80 c2 3.90 4.00 y1 0.65 0.75 e 0.50 bsc y2 2.70 2.80 x1 0.20 0.30 notes: general 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 4. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. a 2 x 2 array of 1.10 x 1.10 mm openings on a 1.30 mm pitch should be used for the center pad. card assembly 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per t he jedec/ipc j-std-020 specification for small body components. ?
cp2130 26 rev. 0.7 d ocument c hange l ist revision 0.5 to revision 0.6 ? updated pin configuration functions for gpio.6 and gpio.7. revision 0.6 to revision 0.7 ? moved vbus to a separate row and updated the specification in table 9, ?absolute maximum ratings*,? on page 8. ? added v pp voltage specification to table 7, ?otp rom electrical characteristics,? on page 7. ? updated "7. voltage regulator" on page 18 to add absolute maximum voltage on vbus requirements in self-powered systems. ? updated measured throughput numbers in table 10, ?typical spi throughput,? on page 11.
cp2130 rev. 0.7 27 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal soluti ons. silicon labs' extensive patent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibili ty for errors and omissions, and disclaim s responsibility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warran- ty, representation or guarantee regarding t he suitability of its products for any par ticular purpose, nor does silicon laborato ries assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, in cluding without limitation consequential or incidental damages . silicon laboratories products are not designed, intended, or authorized for use in applica tions intend- ed to support or sustain life, or for any other application in which the failure of the silicon laboratories product could crea te a situation where personal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unaut horized application, buyer shall indemnify and hold silicon laboratories harmle ss against all claims and damages.

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